1. Technical Field
The present invention relates to a processing support device, method and a computer readable storage medium, and a semiconductor fabrication support device and method, and more specifically relates to a processing support device, method and a computer readable storage medium, and a semiconductor fabrication support device and method for a fabrication line that applies predetermined processing to targets with predetermined equipment.
2. Related Art
Systems of equipment for applying predetermined processing to plural numbers of semiconductor wafers constituting individual lots (lot processing) fall into two categories. One category is batch systems that simultaneously process all the semiconductor wafers included in a lot at one time, and the other category is single-wafer systems that process the semiconductor wafers included in a lot one at a time.
For a piece of equipment in any kind of system, a processing duration required for processing a lot may be ascertained by, for example, measuring a duration from when a start signal indicating that lot processing has started is inputted to when an end signal indicating that the lot processing has finished is inputted. A duration required for lot processing, a schedule of processing to be conducted before and after the lot processing, and suchlike may be administered using a duration that is measured in this manner.
For example, Japanese Patent Application Laid-Open (JP-A) No. 6-291006 discloses a technology with the object of improving fabrication performance of a semiconductor fabrication line. This technology predicts a completion duration of processing of a step on the basis of previous processing durations, and starts processing of a previous step so as to be in time for the completion duration. However, JP-A No. 6-291006 does not specifically disclose how a processing completion duration of a step is predicted on the basis of previous processing durations. Consequently, specifying the processing start time of the previous step is difficult in practice.
JP-A No. 2001-209421 discloses a technology with the object of predicting a completion duration of lot processing. This technology defines processing durations of respective operations in accordance with structures and operations of equipment and, through complex calculations, predicts a duration of lot processing.
However, although the technology recited in JP-A No. 2001-209421 may predict a completion duration of lot processing, extremely complicated calculations are required for predicting the processing duration. Therefore, if support is conducted using the processing recited in JP-A No. 2001-209421 to perform lot processing in accordance with a scheduled duration, complicated calculations must be carried out.
Apart from cases of executing processing relating to semiconductors, similar problems also arise when, for example, the technology recited in JP-A No. 2001-209421 is used when some kind of processing is applied to processing targets other than semiconductors.